const csr = @import("riscv").csr;
const os = @import("../os.zig");
const proc = os.proc;

pub var ticks: usize = 0;
pub var lock: os.Lock.Spin = .init("clock");

/// Must be called with interrupts disabled
pub fn intr() void {
    if (proc.Cpu.id() == 0) {
        lock.acquire();
        defer lock.release();

        ticks +%= 1; // wrapping addition
        proc.wakeup(&ticks);
    }

    // ask for the next timer interrupt. this also clears the interrupt request.
    csr.stimecmp.write(csr.time.read() + os.arch.qemu.TIMER_TICK_INTERVAL);
}
